A new Pulse VHDL simulator open source project has appeared on GitHub, written by Óscar Grimal in C++ under an MIT licence, and it aims to deliver a complete toolchain from compiler through to waveform output without depending on any variant of the long-established ghdl.
A fresh toolchain from the ground up
Pulse is still very much a work in progress, but the scope Grimal has laid out is worth paying attention to. The project covers the full pipeline: parsing and compiling VHDL source, running the simulation, and presenting output to the user. That waveform output arrives via a text-based user interface, or TUI, rather than a conventional graphical waveform viewer. It is a pragmatic choice that keeps the tool genuinely cross-platform without dragging in a thicket of graphical dependencies.
On the dependency front, Pulse keeps things admirably lean. You need a C++20-capable compiler and CMake, and that is essentially it. For anyone who has wrestled with getting a simulation environment running on an unfamiliar machine, that minimal footprint is a genuine selling point. C++20 is now well supported across GCC, Clang, and MSVC, so the barrier to building from source is lower than it once would have been.
Where Pulse VHDL simulator support currently stands
VHDL is not a small language. Once you factor in the associated standard library, the specification runs to considerable depth, and implementing it comprehensively takes real effort. At present, Pulse supports basic IEEE packages and types, which is enough to run straightforward designs, but more advanced constructs are still absent. Default values are not yet supported, and that will limit what existing VHDL code can be fed straight into the simulator without modification.
The roadmap laid out in the project’s GitHub Readme is candid about what remains to be done. Generics are on the list, as are additional types and a more capable simulation engine. These are not peripheral features in VHDL; generics in particular are central to writing reusable, parameterisable components, so their absence is a meaningful gap for anything beyond tutorial-level work. Knowing they are explicitly on the roadmap, rather than quietly deferred, is reassuring.
Mixed-language plans and the SystemVerilog question
One of the more ambitious items in the roadmap is mixed-language support, specifically the ability to simulate designs that combine VHDL with Verilog. Mixed-language simulation has long been a practical necessity in larger projects, where IP blocks and team conventions rarely align neatly around a single HDL. Pulse intends to support it.
SystemVerilog, however, appears to be a lower priority, which will surprise few people who follow open-source EDA tooling. SystemVerilog’s verification extensions add substantial complexity to any simulator’s front end, and it is a pattern repeated across the open-source landscape that SystemVerilog tends to receive less attention than its two older siblings.
How it sits alongside ghdl
The question that will occur to most VHDL users immediately is how Pulse compares to ghdl, the simulator that has dominated open-source VHDL work for years. Ghdl has had well over a decade of development behind it, broad language coverage, and integration with tools such as Yosys for synthesis flows. Pulse is not trying to replace that today; it is, by its author’s own description, still in progress.
What Pulse offers right now is a different architectural starting point, a from-scratch C++ implementation with a minimal dependency tree and a TUI-first output philosophy. As language coverage grows and the simulation engine matures, a direct comparison will become more instructive. The MIT licence means anyone can contribute, fork, or embed the code, which at least keeps the project’s trajectory open.
The GitHub Readme roadmap is the clearest indicator of what comes next: generics, broader type support, the enhanced simulation engine, and eventual Verilog interoperability. Each of those milestones will mark Pulse VHDL simulator progress in a measurable way.
